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Abstract

DRAM read disturbance, like RowHammer and RowPress, is a critical robustness issue where accessing DRAM can cause unintended bitflips in other unaccessed DRAM locations. DRAM read disturbance bitflips significantly impact the safe, secure, and reliable operation of DRAM-based computing systems. Many prior works extensively perform experimental characterization of DRAM read disturbance bitflips and propose mitigation techniques based on the empirical characterization results. Some other device-level works study the underlying physical mechanisms of DRAM read disturbance bitflips, but these studied mechanisms do not fully explain all the empirical observations from experimental characterization studies. Our goal in this paper is to bridge the gap between experimental characterization and device-level modeling and understanding of RowHammer and RowPress to provide a principled foundation for future works on understanding, characterizing, and mitigating DRAM read disturbance. To this end, we first identify and demonstrate the gaps and inconsistencies between the current understanding of the physical mechanisms of RowHammer and RowPress from existing device-level modeling works and experimental characterization of RowHammer and RowPress bitflips. We focus on three most fundamental metrics of RowHammer and RowPress read disturbance bitflips that should map to the first-order underlying physical mechanisms: 1) bitflip directions, 2) the bitflip counts, and 3) the minimum number of aggressor row activations to trigger the first bitflips (i.e., AC min). Second, we present a comprehensive and rigorous set of TCAD simulations that match the observed phenomena from experimental characterizations of RowHammer and RowPress bitflips. From our results, we 1) summarize a set of updated device-level error mechanisms for understanding RowHammer and RowPress bitflips, and 2) identify key modeling and simulation parameters that significantly affect whether simulation results match real-chip characterization. We discuss the implications of our findings on 1) rigorous, comprehensive, and efficient experimental characterization methodologies of DRAM read disturbance bitflips, and 2) the designs of DRAM read disturbance mitigation techniques.